The present invention generally relates to processing a semiconductor substrate to reduce the dielectric constant of an innerlayer dielectric. In particular, the present invention relates to providing a void in an innerlayer dielectric thereby reducing the dielectric constant.
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements called interconnect lines (interconnects). Interconnects are patterned from layers of electrically conductive materials (e.g., metals such as aluminum and/or copper, doped polysilicon, etc.) formed on the surface of a silicon wafer. Multiple layers (or levels) of closely-spaced interconnects allow an increase in the density of devices formed on semiconductor wafers. Electrical separation of stacked interconnect layers is achieved by placing an electrically insulating material (i.e., interlevel dielectric layer) between the vertically spaced interconnect layers. Electrical separation of adjacent interconnect lines is achieved by placing an electrically insulating material (i.e., innerlayer dielectric) between the conductive interconnect lines.
Many types of materials are employed as insulating materials. Examples include oxides, silicates, nitrides, low k materials, and air. These insulating materials have different properties and characteristics; thus, different insulating materials are used depending upon the requirements of a given environment. Although air lacks the structural integrity of oxides, silicates, nitrides, and low k materials, air is the cheapest and has the lowest dielectric constant (about 1). Therefore, in many instances it is desirable to employ air as an insulating material. The requirement of structural integrity, however, limits the extent to which air is employed in semiconductor manufacturing.
In very large scale integrated (VLSI) circuit devices, several wiring layers each containing numerous interconnect lines are often required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure typically consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. With the trend to higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow, such as about 0.18 microns and smaller. In addition, when the height of the conductive lines is increased, it is more difficult to fill gaps between the lines, especially when the aspect ratio is 2 to 1 or greater with a gap distance of 0.25 microns or smaller.
In order to satisfy increasingly higher density requirements, the dimensions of integrated circuits are continuously reduced and, hence, the line widths of the conductors decreased into the submicron range. While the conductors become narrower and narrower, and the space between conductors becomes narrower and narrower, the stresses imposed upon the conductive material increase, thereby resulting in a high failure rate. Many of these failures stem from the effects of voids that generate stress migration as a result of thermal stresses caused by exposure at different temperatures, air in contact with the conductive lines, or to subsequent processing. These voids, which can range from 0.05 microns to about 10 microns or more, when in contact with metal lines can lead to failures causing open circuits.
Referring to FIGS. 1 and 2, this problem is illustrated. In FIG. 1, a substrate 10 is provided with metal lines 12, and an insulator 14 thereover. An air void 16 is positioned between metal lines 12 to increase the insulation therebetween. FIG. 2 shows the effects of thermal processing on the structure of FIG. 1. In particular, the air void 16 undesirably shifts so that it contacts one of the metal lines 12 due to the effects of semiconductor processing, such as repeated thermal cycles or etching. Consequently, stress is imposed upon the metal lines 12 as well as upon the device once fabrication is completed.
The present invention provides an innerlayer dielectric structure and method of making such a structure wherein an air void is positioned between metal lines, thereby providing excellent insulation properties. As a result of the present invention, improved insulation is achieved because the use of air, with its low dielectric constant, is employed as an innerlayer dielectric with minimal risks of deleterious air void shifting. Also as a result of the present invention, the use of air as an innerlayer dielectric is enabled despite the use of aggressive processing steps after formation of the innerlayer dielectric.
One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer.
Another aspect of the present invention relates to a method of forming an innerlayer dielectric having a dielectric constant of about 1, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal silicon nitride layer over the substrate and metal lines, the conformal silicon nitride layer having a substantially uniform thickness from about 250 xc3x85 to about 5,000 xc3x85; forming a first insulation layer over the conformal silicon nitride layer, the first insulation layer containing an air void positioned between two metal lines; at least one of thinning and planarizing the first insulation layer; and forming a second insulation layer over the first insulation layer.
Yet another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 xc3x85 to about 5,000 xc3x85; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.
Still yet another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal silicon nitride layer over the semiconductor substrate and metal lines, the conformal silicon nitride layer having a substantially uniform thickness from about 1,000 xc3x85 to about 3,000 xc3x85; a first insulation layer over the conformal silicon nitride layer, the first insulation layer containing an air void positioned between two metal lines; and a second insulation layer having a thickness from about 2,500 xc3x85 to about 10,000 xc3x85 over the first insulation layer.